The Impact of Wafer Topography Issues on The Next Generation Processes

摘要

The impact of nanotopography of silicon wafer on the polishing of silicon-oxide films on the wafers was quantitatively evaluated. Oxides remaining after the polishing have the thickness variations that depend on both nanotopography features and pad stiffness. It is concluded that high performance in the STI-CMP process can be achieved by improving nanotopography and using pads of optimal stiffness. To obtain the satisfactory patterning performance in the lithography process step, it is shown that chucked-wafer flatness is one of key factors to be analyzed and improved. We succeeded to measure wafer flatness, chuck flatness, and chucked-wafer flatness, separately, and found that the chucked-wafer flatness was affected by the interaction between wafer backside surface and pin-chuck surface. It is shown that the interaction mechanism should be clarified.