Estimating PLC logic program reliability

摘要

In earlier research we developed a theory for predicting the reliability of conventional sequential programs based on an estimate of residual faults. This paper describes how the theory was applied to a realistic industrial example containing a known number of faults. The industrial example was implemented in a PLC application language where the program is represented by a network of logic gates (e.g. AND and OR gates). To make a residual fault estimate, our fault estimation method had to be adapted to apply to logic networks. The previous estimation method relied on a measurement of code coverage, and this had to be replaced by a measurement of logic network coverage. Several different measures of logic coverage were evaluated, including coverage of input values, output values, and input-output pair values. Using the residual fault estimate and information about the testing applied, a reliability bound was calculated and we assessed the sensitivity of the bound to changes in the operational profile.