Reduced Redundant Arithmetic Applied on Low Power Multiply-Accumulate Units

摘要

We propose a new redundant approach on designing multiply-accumulate units for low power. State of the art implementations make use of redundant registers to obtain low delay times by moving any carry propagate adder out of the operation cycle. Our contribution is optimizing the level of redundancy by adjusting the size of the carry register. This optimization is performed by a VHDL generator, creating a carry save reduction tree meeting given delay constraints. This generator uses a delay-driven, list-based algorithm, optimized by synthesis timing results. With this method, the carry register and final carry propagate adder are shortened. Applying our reduced redundant approach to different sized twos complement multiply accumulate units under low power constraints, we gain delay savings up to 21 percent without increased area or power for 16 bit multiply-accumulate units and up to 6 percent for 32 bit multiply-accumulate units.