Cache-Analyzer: Design Space Evaluation of Configurable-Caches in a Single-Pass

机译：缓存分析器：单遍中可配置缓存的设计空间评估

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Today''s digital systems design requires extensive system- level simulation to ensure that the right architectural trade-offs are made. In platform based designs a large number of platforms models must be executed for tuning the platform for the applicati

机译：当今的数字系统设计需要广泛的系统级仿真，以确保做出正确的架构折衷。在基于平台的设计中，必须执行大量平台模型以针对应用调整平台

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来源
《Rapid System Prototyping (RSP), 2007 18th IEEE/IFIP International Workshop on》|2007年|P.3-9|共7页
会议地点 Porto AlegreBrazil
作者
Silva; A.; Esmeraldo; G.; Barros; E.; Viana; P.;
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cache storage; logic design; abstract transaction-level model; cache-analyzer; configurable-cache design space evaluation; digital systems design; memory cache tuning; memory hierarchy; single-pass cache simulation;

机译：缓存存储；逻辑设计；抽象的交易级模型；缓存分析器；可配置缓存设计空间评估；数字系统设计；内存缓存调整；内存层次；单遍缓存模拟;

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4. Cache-Analyzer: Design Space Evaluation of Configurable-Caches in a Single-Pass [C] . Silva, Andre, Esmeraldo, . 2007

机译：缓存分析器：单遍中可配置缓存的设计空间评估
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Cache-Analyzer: Design Space Evaluation of Configurable-Caches in a Single-Pass

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