A low-power 20Gb/s transmitter in 65nm CMOS technology

摘要

A 20Gb/s transmitter employing an analog filtering pre-emphasis equalization technique is presented. The transmitter dissipates 10mW from a 1.2V supply and occupies 0.01mm². This high-frequency boosting equalization technique allows for compensating channel losses up to 20dB at Nyquist-rate. The prototype was fabricated in 65nm CMOS technology and characterized using lossy cables and 5″ and 10″ FR4 PCB traces.