FPGA based design for motion vector predicton in H.264/AVC encoders targeting HD1080p resolution

摘要

Motion vector coding is an important issue in low bitrate video coding, since it relatively increases the efficiency of modern video encoders. The motion vector prediction exploits the correlation between the motion of neighbor blocks, since they may represent the same object and then present the same movement direction. The motion vector prediction is performed by a difference between the current motion vector and the predictive motion vector (PMV), generated using the neighbor blocks as reference. This way, only the motion vector difference (MVD) is sent to the bit stream. Due to its performance the motion vector prediction is defined as an obligatory tool in the H.264/AVC standard. This work presents a FPGA based hardware architecture for the H.264/AVC motion vector predictor targeting HD1080p resolution. The architecture was described in VHDL and synthesized to Xilinx xc5vlx30 Virtex V FPGA. The results were compared with one motion vector prediction architecture from the literature. Our design has shown better results considering hardware usage and throughput than the related work. Besides, we used a motion estimation and motion compensation architecture composing a whole inter-frame prediction module, to perform a better evaluation of the results generated by our proposed motion vector predictor architecture. The results have shown that our architecture uses few hardware resources and it can process until 52 HD1080p frames per second.