Design of Optimized Modular Multiplier Using Montgomery Algorithm for RSA Cryptosystem

摘要

Modular multiplication plays a vital role in RSA Cryptography and Elliptical Curve Cryptography. We have implemented a 256-bit Modular multi plier using Montgomery Reduction Algorithm in VHDL. The output of the Montgomery multiplier is Z = X~* Y R~(-1) mod M. Our main aim is to calculate the area required for the modular multiplier using Montgomery reduction algorithm. It is a full-featured circuit including Carry save Adders, shift registers, multiplexers, parallel registers component and are too big to fit into a single Altera Stratix Device on the Field Programmable platform, so that we are unable to test them in real hardware. However, each sub-component was simulated in Model-Sim SE 6.0 and Altera Quartus II 8.0 and proved functionally correct.