A High Speed Flash Analog to Digital Converter

摘要

This paper presents the design and implementation of a 4-b Flash Analog to Digital Converter (ADC) in 180nm digital CMOS technology. The proposed flash ADC utilizes resistive ladder logic network, high speed comparators and a encoder logic to convert the given continuous input signal into output binary code. The flash ADC utilizes a novel encoder realized using pseudo dynamic CMOS logic which has been implemented with fewer transistors compared to the previous other techniques. Without the need of time interleaving technique, the proposed ADC is capable of operating at its full sampling rate. The designed flash ADC consumes 0.686mW when operated from a power supply voltage of 1.8V. The operating speed of this circuit is 10GHz and the simulated integral non-linearity error (INL) and differential non-linearity error (DNL) are between 0.1/-0.02LSB and 0.33/-0.12LSB respectively. It occupies an effective area of 0.32mm².