Behavioral Modeling of LDO

摘要

A 1.2 V 40 mA low-dropout regulator (LDO) for system-on-chip applications with 700 mV dropout is designed in Verilog-A. The proposed LDO provides fast line and load-transient responses with temperature-independent operation. The proposed LDO has been designed in Verilog-A using tsmc 65 nm CMOS technology and the total error of the output voltage due to line and load variations is low. The proposed LDO Design can be used to check the functional correctness of the SOC in the AMS verification flow.