Automated diagnosis of HV/LV and floating gate faults in VLSI design

摘要

This paper presents automated methods and CAD programs to trace the connectivity of hierarchical netlists and detect HV/LV connection or floating gate faults in VLSI design. We describe algorithms and data structures for the flattening of a hierarchical netlist as well as detecting faults in a large circuit. The paper describes experimental results and GUI capability to highlight faults in Cadence schematic window.