首页> 外文会议>Proceedings of the 2013 international conference on engineering of reconfigurable systems amp; algorithms >Ersa - Invited Talk/Lecture: Addressing The Challenges Of Hardware Assurance In Reconfigurable Systems
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Ersa - Invited Talk/Lecture: Addressing The Challenges Of Hardware Assurance In Reconfigurable Systems

机译:Ersa-特邀演讲/讲座:应对可重构系统中硬件保障的挑战

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Despite the numerous advantages of nanometer technologies, the increase in complexity also introduces a viable vector for attacking an integrated circuit (IC): a hardware attack, also known as a hardware Trojan. Since such an attack is implemented within the hardware of a design, it is generally undetectable to any software operating on this circuitry. To make matters worse, a hardware attack could be introduced at almost any point in a design's development cycle, be it through third-party intellectual property (IP) licensed for a design, or through unknown modifications made during the fabrication process. This malicious hardware could act as a kill-switch for a vital device, or as a data-leak for sensitive information. Activation would occur at some predetermined time or by a trigger from a malicious agent. An effective method is required to find such unexpected functionality. This paper describes several key challenges to be addressed in order to provide hardware assurance for trustworthy systems. We examine the platform of field programmable gate arrays (FPGAs) both for their potential vulnerability to threats within third-party IP as well as their capability to accelerate the testing of those modules.
机译:尽管纳米技术具有许多优点,但是复杂性的增加也引入了一种可行的媒介来攻击集成电路(IC):硬件攻击,也称为硬件木马。由于这种攻击是在设计的硬件内实施的,因此对于在此电路上运行的任何软件来说,通常是无法检测到的。更糟的是,几乎可以在设计开发周期的任何时候引入硬件攻击,无论是通过许可设计的第三方知识产权(IP)还是在制造过程中进行未知的修改。这种恶意硬件可能充当重要设备的“致命开关”,或者充当敏感信息的数据泄漏。激活将在某个预定时间或由恶意代理触发而发生。需要一种有效的方法来找到这种意外的功能。本文描述了要为可信赖的系统提供硬件保证而要解决的几个关键挑战。我们检查了现场可编程门阵列(FPGA)的平台,了解它们对第三方IP威胁的潜在脆弱性以及加速这些模块测试的能力。

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