FPGA Implementation of a High-Speed Stereo Matching Processor Based on Recursive Computation

摘要

This paper presents a processor architecture for high-speed stereo matching based on SAD (Sum of Absolute Differences) computation. To reduce its computational complexity, an hardware-oriented algorithm exploiting common intermediate results between SADs is proposed. When designing the image processor, one most critical issue is to find the scheduling that reduces the data transfer amount between the external image memory and the on-chip local memory modules while maintaining the degree of parallelism. For the purpose, we propose the scheduling that exploits disparity-level parallelism although conventional scheduling approaches exploits window-level parallelism. The result of the FPGA implementation shows that the frame rate of 200 frames/sec is achieved by using 64 PEs implemented on a single ALTERA Stratix EP1S40F1020C7 at 80MHz for VGA images.