An Asynchronous Field-Programmable VLSI Using LEDR/4-Phase-Dual-Rail Protocol Converters

摘要

This paper presents a novel architecture that combines 4-phase dual-rail encoding and Level-Encoded Dual-Rail (LEDR) encoding. 4-phase dual-rail encoding is suitable for function units because of its small area, while LEDR encoding is suitable for programmable interconnection resources because of its high throughput and low power. Area-efficient protocol converters are proposed based on transistor-level optimization. The proposed architecture is designed using a 90nm CMOS process. Compared to the 4-phase dual-rail architecture, the throughput and the power consumption are respectively by 45% higher and by 36% lower with almost the same transisitor count. Compared to the LEDR architecture, the transistor count is by 35% lower with almost the same throughput and power consumption.