A Specification Methodology for the Optimal Layout of a 2-Stage Interconnect Bus for Massively Parallel Architectures

摘要

The upcoming technology of Field Programmable Gate Arrays is now reaching applications in the domain of High-Performance Computing. Due to this fact computer architecture becomes more and more diverse, up to parallel architectures consisting entirely of FPGAs as processing elements. Depending on the design approach some of these custom computing machines require a custom interconnect bus. Here the 2-stage shared bus is of great importance due to the structural similarity to the common mechanical connection and mounting concept of cards which are plugged into a backplane. The performance of this bus depends on both, the logical design and the Printed-Circuit-Board layout specification. Critical parameters are identified and a methodology is shown how to optimize a 2-stage interconnect bus in terms of specifying the PCB-layout. Finally an implementation is presented where this methodology has been applied.