FPGA Based Control Loops for THD Minimization and Precise RMS Control in Sinewave Inverters for UPS and Emergency Power Supplies

摘要

Low cost sinewave output inverters can be digitally controlled either by using DSP or FPGA subsystem based control loops. With the design targets aimed at total harmonic distortion (THD) minimization and precise RMS output value control, FPGA based design approach can be hardware efficient, and with the possibility of porting into less complex CPLD platforms for commercial designs. In a case where a PWM waveform with flexible timing could be generated using a digital potentiometer array, the FPGA hardware could simply calculate a fundamental frequency component, with an efficient hardware algorithm, and then use template matching techniques etc for overall THD minimization without calculating individual Fourier components (such as in a DSP based approach), and independently calculating the RMS value of the output waveform. The paper presents the design approach used in a proof of concept project using an Altera FPGA development board, with the possibility of hardware minimization towards a lower gate count FPGA based hardware. Attractive features of this approach are fast implementation, lower cost, shorter design cycles and speed of the loop with the possibility of power quality monitoring, for a case with a complex FPGA subsystem.