Analysis of high-bandwidth low-power microring links for off-chip interconnects

摘要

Performance scalability of computing systems built upon chip multiprocessors are becoming increasingly constrained by limitations in power dissipation, chip packaging, and the data throughput achievable by the interconnection networks. In particular, today's systems based on electronic interconnects suffer from a growing memory access bottleneck as the speed at which processor-memory data can be communicated out of the chip package is severely bounded. Silicon photonics provide a CMOS-compatible solution for integrating high bandwidth-density off-chip optical I/O which can overcome some of these packaging limitations while adhering to pJ/bit-scale power efficiency requirements. Microrings in particular pose an attractive option for realizing optical communication functionalities due to their low footprint, low power dissipation, and inherent WDM-suitability due to their wavelength-localized operation. We analyze a terabit-per-second scale microring-based optical WDM link composed of current best-of-class devices. Our analysis provides quantitative measures for the maximal achievable bandwidth per link that could be reasonably realized within several years. We account for the full optical power budget to determine the achievable bandwidth as well as to enable a power consumption analysis including transmit and receive circuitry, photonic-device power dissipation, and laser power. The results highlight key device attributes that require significant advancement and point out the need for improvements in laser wall-plug efficiencies to provide sub-pJ/bit scale optical links.