Metal layer resist process optimization by design of experiment

摘要

Abstract: The lithography processes for the metal layers of stacked DRAM have normally been considered as one of the most important steps to determine the chip yield performance. The severe topography step-height on the metal resist processes normally leads to an insufficient UDOF for production. The Taguchi design of experiment (DOE) method is chosen in this study to optimize the resist processes on metal layers with a 1.0 $mu@m topography step. The resist process parameters are arranged into the orthogonal arrays and to experimentally determine the optimized conditions for resist patterned over the severe topography step-height with 1.2 $mu@m pitches. The important factors controlling the process window are reported in the paper. An increase of 4 dB in S/N response, which corresponds to an increase of 0.4 $mu@m in DOF and 6% in exposure window, is achieved by using the design of the experiment. Furthermore, the control factors to determine the optimized process conditions for thick resist processes on metal topography wafers can be quite different from those for thin resist processes on bare silicone wafers. !0