1 Gbit/s serial data link using multi level signaling for fast readout front end or 3D-IC applications

摘要

A high-speed serial link has been developed for data acquisition for s-LHC experiment upgrade at CERN or between tiers in 3D-IC application. To reduce the required bandwidth of the channel for a given bit rate and the maximum on-chip clock frequency a current multi level signaling was used. The circuit specifications concerning the number of analog levels used (Pulse Amplitude Modulation 16-bit) were inspired by the 10GBASE-T standard in current mode. The circuit frequency is 250 MHz for a 1Gbit/s data transmission. The analog and digital voltage supply is 1,6 V. This data link is implemented in IBM 130 nm 8RF CMOS process.