On Clock Frequency Effects in Side Channel Attacks of Symmetric Block Ciphers

摘要

Differential power analysis (DPA) becomes cumbersome when the analyzed traces are misaligned. The misalignment can be caused by deliberately inserting dummy wait states, random CPU stalls, or a random clock. In this paper we discuss clock frequency effects in random clock equipped cryptosystems and show that the power traces captured accordingly feature not only shifts in time domain, but also changes in the amplitude domain. These changes are more significant when increasing the base clock frequency. Therefore, trace preprocessing before performing an effective power analysis attack is necessary. We thus discuss first some existing alignment methods in time domain and then propose a method to normalize the horizontally aligned traces in the amplitude domain. As a demonstrator for these effects, a random clock armed AES-128 cryptosystem will be attacked at 2, 7, and 12 MHz base clock frequency, respectively. The experiments clearly unveil that at higher clock frequencies just a horizontal alignment is not sufficient. It is therefore necessary to preprocess the horizontally aligned traces in the amplitude domain too, which can neutralize the observed clock frequency effects and may greatly enhance a subsequent DPA attack.