Dept. of Electr. Comput. Eng., Univ. of California, Davis, CA;
CMOS integrated circuits; microprocessor chips; multiprocessor interconnection networks; telecommunication links; wireless LAN; -synchronous on-chip interconnection network; 802.11a WLAN baseband receiver; CMOS; DSP platform; GALS many-core heterogeneous; bit rate 54 Mbit/s; dedicated-purpose accelerators; frequency 594 MHz; interconnection link; interconnection links; local oscillators; power 12.18 mW; power 123.18 mW; power 174.76 mW; processors; shared memory modules; size 65 nm; small programmable cores; source-sy;
机译:适用于GALS多核平台的可重构源同步片上网络
机译:从网络角度看片上网络:多核互连中的拥塞和可伸缩性
机译:异构互连网络管理平台
机译:GALS许多核心异构DSP平台,具有源同步片上互连网络
机译:为未来的多核芯片多处理器设计芯片上互连网络。
机译:基于CBP-Mesh和Torus互连的片上通信的新型By-by-pass-Torus架构
机译:I(Re)2-WiNoC:探索可扩展的无线片上微网络,用于异构嵌入式多核soC