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Current Conduction Mechanism for Low-molecular Organic Nonvolatile Memory

机译:低分子有机非易失性存储器的电流传导机理

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Organic devices fabricated with a top metal layer/conductive organic layer/middle metal layer/conductive organic layer/bottom metal layer structure have been reported to demonstrate nonvolatile memory behavior such as an after writing (I_(on))/after erasing (I_(off)) performance of > 1 × 10~1 and a response time of ~10 ns, when the organic conductive layers were AIDCN (2-amino-4, 5-imidazoledicarbonitrile), Alq_3 (Aluminum tris(8-hydroxyquinoline)), or α-NPD. We fabricated an organic nonvolatile memory device with a structure of α-NPD/Al nanocrystals surrounded by Al_2O_3/α-NPD/Al, where α-NPD was N,N'-bis(1-naphthyl)-1,1'biphenyl4-4' diamine. A layer of Al nanocrystals, confirmed by a 1.25-MV high voltage transmission-electron-microscope, was uniformly produced between the a-NPD layers by Al layer evaporation at 1.0 ?/sec on the α-NPD followed by O_2 plasma oxidation. We confirmed a conduction bistability of ~10~2 and a threshold voltage for a set state of 3 V. Al nanocrystals surrounded by amorphous Al_2O_3 were formed in the a-NPD. They presented seven different reversible current paths for an electron charge or discharge on the nanocrystals. The current slightly increased with an applied bias from 0 V to V_(th), (a high resistance state (I_(off))), abruptly increased with an applied bias from V_(th), to V_p, decreased with an increasing applied bias from V_p to V_e (a negative differential resistance (NDR) region), and slightly increased with an applied bias above V_e. After sweeping the first applied voltage from 0 to 10 V (erase), a second applied bias was swept from 0 to V_p (program), where the current followed a high resistance state (I_(off)). Next, a third applied bias was swept from 0 to V_p again, where the current followed a low resistance state (I_(on)). Surprisingly, the ratio of I_(on) to I_(off) was ~1×10~2, which is enough current difference to be nonvolatile memory behavior. These I-V characteristics under a positive applied bias were symmetrically repeated under a negative applied bias. All the current sweeping paths were reproducible and symmetrical for an applied bias polarity. In particular, our device demonstrated multi-level nonvolatile memory behavior. It also revealed the current conduction mechanism for each of its operation regions. We observed that the high resistance and low resistance regions followed space-charge-limited current conduction, the V_(th) to V_p and V_(NDR) to V_e regions followed precisely thermionic-field-emission current conduction, and the above V_e regions followed space-charge-limited current conduction.
机译:已经报道了用顶部金属层/导电有机层/中间金属层/导电有机层/底部金属层结构制造的有机器件表现出非易失性存储行为,例如写入后(I_(on))/擦除后(I_(当有机导电层为AIDCN(2-氨基-4,5-咪唑二甲腈),Alq_3(三(8-羟基喹啉铝))时,性能> 1×10〜1,响应时间为〜10 ns,或α-NPD。我们制造了一种有机非易失性存储器件,其结构为被Al_2O_3 /α-NPD/ Al包围的α-NPD/ Al纳米晶体,其中α-NPD为N,N'-双(1-萘基)-1,1'biphenyl4- 4'二胺。通过在α-NPD上以1.0l / sec的Al层蒸发然后O_2等离子体氧化,在a-NPD层之间均匀地产生由1.25-MV高压透射电子显微镜确认的Al纳米晶体层。我们确认了导电双稳态为〜10〜2,阈值电压为3 V的设定状态。在a-NPD中形成了被非晶Al_2O_3包围的Al纳米晶体。他们为纳米晶体上的电子充电或放电提供了七种不同的可逆电流路径。电流从0 V施加到V_(th)(高电阻状态(I_(off)))时,偏置电流略有增加;随着V_(th)施加到V_p的偏置,电流急剧增大。从V_p到V_e(负差动电阻(NDR)区域)的偏置,并且随着施加的偏置高于V_e而略有增加。在将第一个施加的电压从0扫描到10 V(擦除)之后,将第二个施加的偏置从0扫描到V_p(编程),其中电流遵循高电阻状态(I_(off))。接下来,再次施加的第三偏压从0扫至V_p,电流遵循低电阻状态(I_(on))。令人惊讶的是,I_(on)与I_(off)之比为〜1×10〜2,这足以使电流差成为非易失性存储行为。在负施加偏压下对称地重复这些在正施加偏压下的IV特性。对于施加的偏置极性,所有电流扫描路径都是可重现的且对称的。特别是,我们的设备展示了多级非易失性存储器行为。它还揭示了其每个工作区域的电流传导机制。我们观察到高电阻和低电阻区域遵循空间电荷限制的电流传导,V_(th)至V_p和V_(NDR)至V_e区域精确地遵循热电子场发射电流传导,而上述V_e区域遵循空间电荷限制电流传导。

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  • 来源
    《MRS spring meeting symposium》|2008年|p.1-5|共5页
  • 会议地点 San Francisco, CA(US)
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    Department of Computer Science and Engineering Hanyang University Nano SOI Process Laboratory Room #101 HIT Hanyang University 17 Haengdang-dong Seoungdong-gu Seoul 133-791 Korea Republic of;

    Department of Computer Science and Engineering Hanyang University Nano SOI Process Laboratory Room #101 HIT Hanyang University 17 Ha;

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