Verification of embedded system's specification using collaborative simulation of SysML and simulink models

摘要

The authors propose an extension of SysML which enables description of continuous-time behavior. The authors also develop its execution tool integrated on Eclipse-based platform by exploiting co-simulation of SysML and MATLAB / Simulink. To demonstrate the effectiveness of the tool and the extension to SysML in verifying specifications of an embedded system, we create a sample model and analyze its execution results by checking constraints under a test case.