Analog transaction level modeling

摘要

Due to the better technology scaling of digital blocks compared to analog blocks, more and more parts of the analog implementation of modern IC designs are shifted to the digital domain, leading to mixed signal designs. However, no verification methodology, that considers the functional verification task of digital and analog blocks holistically, exists so far, whereas many verification methodologies for the digital domain have arisen over time; the newest being the Universal Verification Methodology (UVM) standard [1].