Development of generic verification environment based on UVM with case study on HMC controller

摘要

ASIC/SoC verification is one of the most important task in digital design world. A survey tells that 60 to 70 % of total design time is consumed by verification only. Different companies adopt different verification methodology till UVM comes into the picture, which is the best solution to overcome drawbacks of previous methodologies. This paper presents generic verification environment architecture based on UVM and it also presents how different component are connected with each other. As a case study, generic design of Hybrid Memory Cube(HMC) memory controller is presented with some test scenario of verification.