首页> 外文会议>Data Compression Conference >Algorithms and Hardware Structures for Unobtrusive Real-Time Compression of Instruction and Data Address Traces
【24h】

Algorithms and Hardware Structures for Unobtrusive Real-Time Compression of Instruction and Data Address Traces

机译:用于不引声实时压缩指令和数据地址迹线的算法和硬件结构

获取原文

摘要

Instruction and data address traces are widely used by computer designers for quantitative evaluations of new architectures and workload characterization, as well as by software developers for program optimization, performance tuning, and debugging. Such traces are typically very large and need to be compressed to reduce the storage, processing, and communication bandwidth requirements. However, preexisting general-purpose and trace-specific compression algorithms are designed for software implementation and are not suitable for runtime compression. Compressing program execution traces at runtime in hardware can deliver insights into the behavior of the system under test without any negative interference with normal program execution. Traditional debugging tools, on the other hand, have to stop the program frequently to examine the state of the processor. Moreover, software developers often do not have access to the entire history of computation that led to an erroneous state. In addition, stepping through a program is a tedious task and may interact with other system components in such a way that the original errors disappear, thus preventing any useful insight. The need for unobtrusive tracing is further underscored by the development of computer systems that feature multiple processing cores on a single chip. In this paper, we introduce a set of algorithms for compressing instruction and data address traces that can easily be implemented in an on-chip trace compression module and describe the corresponding hardware structures. The proposed algorithms are analytically and experimentally evaluated. Our results show that very small hardware structures suffice to achieve a compression ratio similar to that of a software implementation of gzip while being orders of magnitude faster. A hardware structure with slightly over 2 KB of state achieves a compression ratio of 125.9 for instruction address traces, whereas gzip achieves a compression ratio of 87.4. For data address traces, a hardware structure with 5 KB of state achieves a compression ratio of 6.1, compared to 6.8 achieved by gzip.
机译:计算机设计人员广泛使用指令和数据地址迹线,以便对新架构和工作负载表征的定量评估,以及用于程序优化,性能调整和调试的软件开发人员。这种迹线通常非常大并且需要被压缩以减少存储,处理和通信带宽要求。然而,预先存在的通用和痕量的压缩算法设计用于软件实现,不适合运行时压缩。在硬件运行时压缩程序执行跟踪可以在没有任何与正常程序执行的情况下提供对系统的行为的洞察。另一方面,传统调试工具必须经常停止程序以检查处理器的状态。此外,软件开发人员通常无法访问导致错误状态的整个计算历史。此外,逐步通过程序是繁琐的任务,并且可以以这样的方式与其他系统组件相互作用,使得原始错误消失,从而防止任何有用的洞察力。通过在单个芯片上发布多个处理核的计算机系统,可以进一步强调对不引声跟踪的需求。在本文中,我们介绍了一组用于压缩指令和数据地址迹线的一组算法,其可以容易地在片上迹线压缩模块中实现,并描述相应的硬件结构。建议的算法进行了分析和实验评估。我们的结果表明,非常小的硬件结构足以实现与GZIP的软件实现类似的压缩比,同时速度更快。具有略微超过2kB状态的硬件结构实现了指令地址迹线的压缩比为125.9,而GZIP则达到87.4的压缩比。对于数据地址迹线,与通过GZIP实现的6.8相比,具有5 kB状态的硬件结构实现了6.1的压缩比。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号