In this paper, a novel design for the domino XOR gate is presented. The proposed domino gate restructures the traditional domino XOR gate into a hybrid of PTL and CMOS circuits. The result is a reduced number of MOSFETs compared to the traditional design which in turn reduces the power consumption and PDP of the gate by 18% and 6% respectively at the cost of 14% increase in delay of the gate. The proposed design simulated at 1 GHz using HSPICE on PTM 16 nm node. The simulation results of two application of the XOR gate, the binary to gray converter and the parity checker are included. The proposed domino XOR gate is compared to other XOR designs in 16 nm node.
展开▼
