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DTCO Launches Moore’s Law Over the Feature Scaling Wall

机译:DTCO通过特征缩放墙推出Moore的定律

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Instead of marching from one crisply defined technology node to the next with an uncertain timeline, industry is transitioning toward annual technology updates driven by a schedule, but with an uncertain transistor density increase. Full node updates are expected every other year, with "half-node" updates in between. Pitch scaling began slowing after the 10nm node and is expected to practically cease by the 1nm node. Despite that, transistor density is expected to continue increasing at a similar pace of 45% density increase per node (or 20% per year) through the 1nm node, fueled by increasingly sophisticated Design-Technology Co-Optimization (DTCO) and Electronic Design Automation (EDA) advances.
机译:由于采用不确定的时间表,而不是从一个清晰度定义的技术节点前进到一个不确定的时间表,而是向计划驱动的年度技术更新,但具有不确定的晶体管密度增加。每隔一年都会预期完整节点更新,其中“半节点”在介于之间进行更新。音高缩放开始在10nm节点后开始放缓,并且预计在1nm节点上几乎停止。尽管如此,预计晶体管密度将继续以每节点(或每年20%)的相似速度继续增加(或每年20%),通过越来越复杂的设计 - 技术协同(DTCO)和电子设计自动化,推动(EDA)进步。

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