Single-Phase Enhanced Phase-Locked Loops Based on Multiple Delayed Signal Cancellation Filters

摘要

A new single-phase (1?) filtering technique based on multiple delayed signal cancellation (MDSC) is proposed for extracting both in-phase and quadrature components of the selected harmonic order of the 1? grid voltage signal. This MDSC technique can be realized in both the direct-form and the recursive-form. In comparison with existing 1? cascaded delayed signal cancellation (CDSC) techniques, this MDSC technique utilizes less memory for the extraction of grid voltage fundamental frequency component. The proposed MDSC filter can be applied as a pre-filter to the enhanced phase-locked loop (EPLL) for the prompt and accurate estimations of the grid voltage information under adverse grid conditions. Both frequency adaptive and non-adaptive MDSC based EPLL schemes are studied in this paper. Experiments are conducted on the MDSC based EPLLs and compared with the CDSC-EPLL under various grid voltage disturbances.