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An Efficient Parallel Mechanism for Highly-Debuggable Multicore Simulator

机译:高度调试多核模拟器的有效并行机制

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Fast multicore simulators are extremely useful in evaluating design alternatives and enabling early software development. Among the state-of-the-art multicore simulators, Simics is a very popular used one both in academia and industry. It has a powerful debugging system, and also provides an accelerator to support multithreaded or distributed simulation. However, this kind of parallel mechanism mainly aims at speed up distributed systems. It is not suitable for the shared-memory multicore systems which are much more commonly used. In this paper, we propose a novel parallel mechanism to improve the simulation speed of shared-memory multicore systems. More importantly, our approach is compatible with other optimizations and exist debugging systems used in Simics. Experimental results show that our parallel approach achieves an average speedup of 9.6× (up to 12.2×) when running SPLASH-2 kernel on a 16-core host machine.
机译:快速多核模拟器在评估设计替代品和启用早期软件开发方面非常有用。在最先进的多核模拟器中,SIMICS是学术界和工业中的一种非常受欢迎的人。它具有强大的调试系统,还提供了支持多线程或分布式模拟的加速器。然而,这种并联机制主要旨在加速分布式系统。它不适用于共享内存多核系统,这些多核系统更常用。在本文中,我们提出了一种新颖的并行机制来提高共享存储器多核系统的模拟速度。更重要的是,我们的方法与其他优化和存在于SIMICS中使用的调试系统兼容。实验结果表明,当在16核主机上运行Splash-2内核时,我们的并行方法实现了9.6×(最多12.2×)的平均速度。

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