Three-Dimensional Simulation of Biaxially Strained Triple-Gate FinFETs: A Method to Compute the Fin Width and Channel Length Dependences on Device Electrical Characteristics

摘要

Multiple gate devices have been considered as an alternative to the miniaturization owing to the better electrostatic control, leading to the short channel effects reduction (1). These devices also provide an increase in the drain current due to the formation of multiple inversion layers, when compared to a planar single gate transistor (1). Triple gate FinFETs are made on a thin and tall layer of silicon surrounded by the gate electrode over the buried oxide and its schematic view is presented at Figure 1. The inversion layers are formed at the sidewalls and the top. However, the carrier mobility depends on the crystallographic orientation. The electron mobility in the surface (100), which is the most common surface for the top gate, is higher than in the surface (110), commonly the sidewall gates (2).