首页> 外文会议>International Symposium on Low Power Electronics and Design >Pipeline stage Unification: A Low-Energy Consumption Technique for Future mobile processors
【24h】

Pipeline stage Unification: A Low-Energy Consumption Technique for Future mobile processors

机译:管道舞台统一:未来移动处理器的低耗耗技术

获取原文

摘要

Recent mobile processors are required to exhibit both low-energy consumption and high performance. To satisfy these requirements, dynamic voltage scaling (DVS) is currently employed. However, its effectiveness will be limited in the future because of shrinking the variable supply voltage range. As an alternative, we previously proposed pipeline stage unification (PSU), which unifies multiple pipeline stages without reducing the supply voltage at a power-saving mode. This paper compares effectiveness of PSU to DVS in current and future process generations. Our evaluation results show PSU will reduce energy consumption by 27-34% more than DVS after about 10 years.
机译:最近的移动处理器需要表现出低能耗和高性能。为了满足这些要求,目前采用动态电压缩放(DVS)。然而,由于缩小可变电源电压范围,其有效性将受到限制。作为替代方案,我们之前提出了管道级统一(PSU),其统一多个管道级,而不会在省电模式下降低电源电压。本文将PSU对当前和未来流程中的DVS的有效性进行了比较。我们的评估结果显示PSU将在大约10年后将能源消耗降低27-34%,而不是DVS。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号