This paper presents a robust methodology for symmetry detection algorithm for integrated circuits (IC) layout designs. Approaches used to detect IC layout symmetry depend on extracting information from the circuit design. A new approach is presented to detect IC layout symmetry between polygons using computer vision. The approach is based on matching between extracted features from the IC layout design as an image. This approach detects translation, scale, rotation and partial symmetries in the IC layout design. In comparison to famous symmetry detection algorithms like SIFT, the new approach succeeds to detect symmetric polygons with higher speed and more accurate results.
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