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Current Crowding and Stress Effects in WCSP Solder Interconnects: A Simulative and Practical Study about the Effects of Major Electromigration Failure Mechanisms in DC and Pulsed-DC Conditions

机译:WCSP焊料互连的当前拥挤和应力效应:关于大型电渗透机制在直流和脉冲直流条件下的影响的模拟和实践研究

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Electromigration (EM) induced failure is inevitable in wafer-level chip scale package microelectronic packages (WCSP), especially with the implementation of lead-free solders. Many factors contribute to EM failure such as joule heating and current crowding. EM can induce void formation, which can eventually lead to open-circuit failure. Due to its nature, EM is a critical failure concern to the microelectronic industry and can be influenced by current conditions. This study examines the failure mechanisms in solder joints implemented in WCSP packages in Direct Current (DC) and DC-pulse current conditions with varying Duty Factors (DF). DF represents the on-off time for DC to flow through the device under test (DUT). Further, a transient simulative study using finite element method (FEM) explores the failure mechanism and investigates the stress development with DC and DF conditions. Findings suggested that a lower duty factor yielded longer time to failure (TTF). Meanwhile, higher pulsed DC DF yielded a lower TTF than DC. This study aims to explain the failure mechanism with each DF. This study aims to explain this phenomenon and suggests the need for further exploration.
机译:电迁移(EM)诱导的故障在晶圆级芯片秤包装微电子封装(WCSP)中是不可避免的,特别是通过实施无铅焊料。许多因素有助于EM失败,例如焦耳加热和当前拥挤。 EM可以引起空隙形成,最终可能导致开路故障。由于其性质,EM是微电子行业的关键失败问题,并且可能受到当前条件的影响。本研究探讨了在直流(DC)和DC脉冲电流条件下在WCSP封装中实现的焊点中的失效机制,具有不同的占空比(DF)。 DF表示DC流过下测试(DUT)的开关时间。此外,使用有限元方法(FEM)的瞬态模拟研究探讨了失效机制并研究了DC和DF条件的应力发展。结果表明,较低的占子因子产生较长的失败时间(TTF)。同时,高脉冲DC DF比DC产生较低的TTF。本研究旨在通过每个DF解释失效机制。本研究旨在解释这种现象,并提出了进一步探索的必要性。

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