A Translator from FDL to SystemVerilog for FPGA Implementation of Fuzzy Inference

摘要

Fuzzy inference has been used in a variety of fields, mainly machine control. Either special-purpose programming language or special-purpose development tool is usually used in software implementation of fuzzy inference. For example, EIAJ (Electronic Industries Association of Japan) standardized FDL (Fuzzy System Description Language) to describe fuzzy inference easily and concisely in Japan in 1996. FDL library and a translator named fdltoc to generate C language were developed at the same time. Therefore, it became possible to convert FDL to C language for software implementation. On the other hand, HDL (Hardware Description Language) is usually used in hardware implementation of fuzzy inference, because there is no hardware development environment for fuzzy inference using IF-THEN type rules and fuzzy sets. However, it is not easy for software engineers to design them with HDL. Moreover, it is not possible to generate HDL by high-level synthesis from C language translated by fdltoc, because C language generated by fdltoc has a description of dynamic memory allocation and uses libraries. This paper proposes a translator from FDL to SystemVerilog named FDLtoSV. The comparison result of software implementation using C language generated by fdltoc and hardware implementation using SystemVerilog generated by FDLtoSV with respect to speed show that the proposed hardware implementation result is about 102 times faster than software implementation result. In addition, its circuit scale is available in a low-cost FPGA.