Reduced Frequency and Area Efficient for Streaming Applications Using Clock Gating and BUFGCE Technology

摘要

Reduced frequency and area-efficient streaming applications using clock gating and BUFGCE technique are presented in the paper. The clock-gating methodology consists of a different microcontroller, logic gates, flip-flop, and buffer. We used four controllers and a logic gate. The experimental results show that area is reduced to 26%, frequency 630.14 MHz, and thereby reducing the dynamic power without any fall in output data.