A Scalable, Sub-1W, Sub-1Ops Clock Skew, Global Clock Distribution Architecture for Intel COFe~(TM) i7/i5/i3 Microprocessors

摘要

This paper describes global clock distribution architecture of Intel Core~(TM) i7/i5/i3 microprocessor family. Highlight of this paper is a pseudo-recombinant clock distribution architecture successfully implemented in 32nm/45nm generation of Core~(TM) i7/i5/i3 processors. This dock distribution topology achieves less than I Ops clock skew while consuming a maximum power of 1 Watt across entire operating voltage and frequency range.