An Efficient and Low-Overhead Chip-to-Chip Interconnect Protocol Design for NOC

摘要

As the scale of the multicore system expands, it may extend to multiple chips with chip-to-chip interconnect, and its data transmission needs to be fast and efficient. Network on chips (NOCs) has become the mainstream structure for distributed multicore connections, while there are few inter-chip protocols for NOC. In this paper, a highly efficient and low-overhead chip-to-chip interconnect protocol design for NOC is proposed, which consists of data link layer, physical layer and flow control mechanism design. By using ZCU102 evaluation kit, we validate our protocol design with various dataflow, achieving up to 10 Gb/s/lane line rate.