An FPGA-based Dead-time Computation Technique for Neutral Point Clamped Multilevel Inverter (NPC-MLI)

摘要

In order to prevent the occurrence of the short circuit between the identical phase-leg semiconductor switches, dead-time is injected in the pulse width modulation (PWM) voltage source multilevel inverters (MLIs). This paper proposes a mathematically formulated dead-time computation technique for neutral-point clamped multilevel inverters (NPC-MLIs) considering the turn ON/OFF timing and delay-time calculation of the phase-leg semiconductor switches. A Mimas-Spartan 6 FPGA device is employed to improve the adaptability of the system in the modern multilevel inverter topologies with enhanced performance such as high-frequency switching and lower power consumption. The experimental results are verified with a Mimas Spartan-6 Field-programmable gate array (FPGA) device, which validates that compared to the earlier-reported works, the proposed technique is the most apposite one to be integrated with the latest development of multilevel inverter topologies with enhanced performance such as lower power consumption and high-frequency switching.