首页> 外文会议>Design, Automation Test in Europe Conference Exhibition >TimingCamouflage: Improving circuit security against counterfeiting by unconventional timing
【24h】

TimingCamouflage: Improving circuit security against counterfeiting by unconventional timing

机译:TimingCamouflage:通过非传统时机提高对伪造的电路安全性

获取原文

摘要

With recent advances in reverse engineering, attackers can reconstruct a netlist to counterfeit chips by opening the die and scanning all layers of original chips. This relatively easy counterfeiting is made possible by the use of the standard simple clocking scheme where all combinational blocks function within one clock period. In this paper, we propose a method to invalidate the assumption that a netlist completely represents the function of a circuit. With the help of wave-pipelining paths, this method forces attackers to capture delay information from manufactured chips, which is a very challenging task because we also introduce false paths. Experimental results confirm that wave-pipelining paths and false paths can be constructed in benchmark circuits successfully with only a negligible cost, while the potential attack techniques can be thwarted.
机译:随着逆向工程的最新进展,攻击者可以通过打开模具并扫描所有原始芯片层来重建网手册到假冒芯片。通过使用标准简单时钟方案,可以实现这种相对容易的假性,其中所有组合块在一个时钟周期内都能函数。在本文中,我们提出了一种方法使网手列表完全代表电路功能的假设使假设无效。借助波浪管线路径,这种方法强制攻击者从制造的芯片捕获延迟信息,这是一个非常具有挑战性的任务,因为我们也引入了虚假路径。实验结果证实,波管管线路径和假路径可以成功地以基准电路构建,仅具有可忽略的成本,而可能会挫败潜在的攻击技术。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号