Large-Scale Numerical Solution of Partial Differential Equations with Reconfigurable Computing

摘要

We describe the shift in paradigm that the algorithm developer must undertake in order to design efficient numerical solutions using Field Programmable Gate Arrays (FPGAs) and reconfigurable computing in general. FPGAs and reconfigurable computing can bring a new dimension to the algorithm design process, with potentially huge gains in algorithm speed, and significant reductions in cost and power consumption. We introduce three levels of parallelism that are possible under this emerging computing paradigm: fine-grained parallelism, coarse-grained parallelism, and algorithm-level parallelism. Furthermore, we illustrate through an example how these levels of parallelism work. Full exploitation of the three levels of parallelism will be a fundamental ingredient for developing the next generation of partial differential equation solvers during the next decade.