High Speed and Highly Cost effective 72M bit density S{sup}3 SRAM Technology with Doubly Stacked Si Layers, Peripheral only CoSix layers and Tungsten Shunt W/L Scheme for Standalone and Embedded Memory

摘要

There have been great demands for higher density SRAM in all area of SRAM applications, such as network and cache standalone memory, and embedded memory of the logic devices. Therefore, aggressive further shrinkage of 6T full CMOS SRAM has been progressed down to 32nm node by even using e-beam lithography and SOI wafer. Nevertheless, for the real production it is not an easy task to solve many fundamental limits of the linear shrink, such as cell instability due to increasing in variations of cell transistor characteristics, standby power consumption, and staggering fabrication yield from 45nm node. Furthermore, there exists uncertainty for the delivery of lithographic tools, such as EUV or super high NA ArF for patterning under 32nm dimensions. Therefore, various alternative embedded memory solutions such as capacitorless 1T DRAM, thyristor type RAM, and magnetic RAM have been proposed to replace planar 6T full CMOS SRAM. Their feasibility for the real mass production is still very uncertain due to adoption of new materials and new operational device physics. However, the S{sup}3 (Stacked Single-crystal Si) SRAM reported in our previous study[1] has been developed on the basis of the well proven Si technology. This technology can be easily implemented into the existing standard logic or memory process without any fundamental changes. The previously reported S{sup}3 SRAM technology had targeted the high density product, such as 288M bit with ArF lithography and 65nm node. However, in this study, the cost effectiveness and the compatibility with the standard planar CMOS process were pursued to utilize the low cost and fully proven technologies, such as KrF lithography, CoSix, and W damascene interconnections in terms of mass production.