A 90nm 6.5GHz 128×64b 4-Read 4-Write Ported Parameter Variation Tolerant Register File

摘要

This paper describes a 128×64b 4-read, 4-write ported register file for 6.5GHz operation in 1.2V 90nm CMOS technology. A wordline underdrive technique combined with local bitline merge NAND whose P/N skew is optimally programmable based on die leakage enables 12% faster performance with 20% reduction in delay variation and 5x reduction in robustness failing dies over optimized high-performance conventional implementation.