A power scalable SAR-ADC in 0.18#x00B5;m-CMOS with 0.5V nano-watt operation

摘要

This paper presents an extremely low-power and low-voltage Analog-to-Digital Converter (ADC) for wireless sensor networks or medical implantable devices. Top plate sampling and bootstrap switch are used to realize ultra low-voltage (0.5V) operation. Configuration of capacitor array which can decrease the number of control bus lines are proposed to reduce the circuit area and power consumption. To further reduce the power consumption, optimal power supply voltages are determined independently for analog blocks and digital blocks considering the tradeoff between the speed and power. Test ADC chip fabricated in 0.18µm-CMOS process has achieved 0.5V, 6nW operation at sampling frequency of 0.4kS/s. The achieved effective number of bit (ENOB) is 7.19-bit. When the supply voltage is increased to 1V, the ADC operates at 820kS/s with power consumption of 30.9µW and ENOB of 7.41-bit.