Scaling hybrid-integration of silicon photonics in freescale 130nm to TSMC 40nm-CMOS VLSI drivers for low power communications

摘要

Within the Ultraperformance Nanophotonic Intrachip Communication (UNIC) program at Oracle, we have been aggressively developing active nanophotonic devices (modulators, detectors, WDM components), circuits, that target ultimate operation of Si photonic links at 15 Gbps and 300 fJ/bit energy consumption. These links are envisioned to operate between computing elements in a large array of chips called a “Macrochip.” We present our recent developments in packaging a marcochip. At each node of the marcrochip is an optical bridge which is a key SiPhotonic component since it contains transceiver functionality, WDM components, and package scaling in 2.5D. High yield hybrid bonding between the bridge and the island chips is necessary to facilitate dense arrays of electrical to optical conversion and additionally requires optical topographical functionality within the package. In our efforts to improve the total aggregate bandwidth, the channel bit rate, the number of channels, and the number of WDM wavelengths needs to be scaled up. At the same time, the device footprint and energy per bit must be significantly scaled down. Packaging results accomplishing this objective will be presented.