A fixed point of DFT/FFT for FPGA platform

摘要

In this paper, the Pipelined Streaming butterfly stage of DFT/FFT is designed including CORDIC and complex algorithm to increase the Performance. This butterfly stage is full use of the register of DSP to transform the complex quantity to the simple Pipelined algorithm and the iteration of CORDIC to compute the trigonometric. The butterfly stage not only save the resources, but also increase the accuracy of result. The simulation show that the butterfly stage is highly the efficiency of compute, accuracy and range.