Challenges in Wafering Processes for Semiconductor and Solar Wafers

摘要

The transition from 50 to 32nm silicon technologies will place strict requirements on semiconductor wafer flatness and nanotopography. Site flatness and shape capability at the edge must improve, as well as the edge characteristics (finish and shape) and quality. As diameter increases from 300 to 450mm, thickness does not scale with wafer diameter leading to a relatively less rigid wafer. This adds additional burden to the task of capability improvement. To be competitive with alternative energy technologies solar wafer manufacture is focused on cost reduction and capability improvement to enable cell-processing optimization. The challenge is to cut thinner wafers with reduced depth of damage, lower TTV and with no micro-cracks. Slicing kerf reduction and abrasive/silicon recovery are options to further reduce cost.