APPLICATION OF ULTRA-RAPID THERMAL ANNEALING FOR ELECTRICAL ACTIVATION FOR NEXT GENERATION MOSFETS

摘要

This paper reports on the ultra-rapid thermal annealing of next generation MOSFETs and their electrical characteristies with device simulation. The junction depth of less than 15 nm was easily realized. However, the device structure parameters and process integration need to be optimized so that the MOSFET can have the required performance. By optimizing the ultra-rapid thermal annealing conditions, device structures and process integration, MOSFET performance can be drastically improved.