The authors describe an LSI implementation of the integer cosine transform (ICT) (10,9,6,2,3,1) and its associated intermediate storage data sequencer for a two-dimensional (2-D) transform. The realization of ICT (10,9,6,2,3,1) on a chip can only be done by optimizing limitations such as die size, pin number and wiring complexity. To reduce the complexity of the ICT chip, a modular architecture is employed to allow data pipelining and parallel processing. Integers of the transform kernel are generated by a decoding process which can reduce the internal wiring. The ICT chip, which can perform a 1-D transform by itself, can perform a 2-D transform together with another LSI gate array data sequencer. The chip set can compute 2-D order-8 ICT in less than 19 mu s.
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