The contribution deals with a binary representation of real numbers. In domain of digital signal processing the number representation is either in fixed-point or floating-point form. There are many processors with fixed or floating-point representation and there are also several blocks used for arithmetical operations in FPGA using fixed or floating point. But generally these blocks do not have a large variability in terms of bit width in consequence of using standardized number formats. The goal of the contribution is mainly to present a simple floating-point unit for FPGAs with user defined formats. In the text the algorithm for multiplication for floating-point representation is presented as well.
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