This paper examines the design issues relating to the implementation of high-performance DSP functions on FPGAs and PLDs. A challenge in implementing such systems on programmable logic is achieving the circuit performance and efficient use of hardware usually associated with ASICs. Using exemplars, we consider how an understanding of the underlying structure of both the design and the target device can result in efficient, high-performance circuits. Appreciation of the design structure also allows targeting of the design and optimisation of the implementation over a range of different programmable logic device families. This is demonstrated by considering design examples on programmable parts from Altera and Xilinx, which perform at high sampling rates for applications such as image processing, or can be implemented using very little hardware in the case of lower bandwidth applications, such as audio.
展开▼
